This invention relates to data communication systems, and more particularly, to a method and mechanism for generating addresses for memory storage of frame data received by a communication switch.
A multiport communication switch may be provided in a data communication network to enable data communication between multiple network stations connected to various ports of the switch. A logical connection may be created between receive ports and transmit ports of the switch to forward received frames to appropriate destinations. Based on frame headers, a frame forwarding arrangement selectively transfers received frame data (packet data) to a destination station.
Data packets received at a receive port of the communication switch are transferred to an external memory and subsequently retrieved and transmitted from a respective transmit port of the switch. Each address of the external memory requires 18-bits and the external memory address would conventionally be determined using 18-bit logic. However, 18-bit logic is complicated, relatively slow and requires a large amount of chip area to implement.
Therefore, it would be desirable to generate the external memory address for the frame data without using complicated 18-bit logic and thus, increase speed and efficiency of chip area utilization.
The invention provides a novel address generator for generating memory addresses for storing data packets received by a multiport data communication system in storage areas of a memory. The data communication system comprises a plurality of receive ports for receiving the data packets and a queue of addresses of a plurality of storage areas in the memory available for storing the received data packets. The address generator includes a first register receiving an address from the queue and providing a first part of the memory address, and a second register counting write cycles to the memory and providing the count result as a second part of the memory address.
The invention provides also a novel method of generating memory addresses for storing the received data packets in storage areas of the memory and comprises inputting an address from the queue of addresses to a first register and providing a first part of the memory address, counting write cycles to the memory with a second register and providing the count result as a second part of the memory address, and combining the first part and the second part to provide the memory address.
In a preferred embodiment, each storage area of the memory stores a predetermined number of data blocks corresponding to one received data packet, and when a number of data blocks representing the one received data packet is greater than the predetermined number, a plurality of storage areas store the number of data blocks.